Switching regulators of the prior art are composed of a switching element and an inductive element, such as a coil, and, by controlling the switching element corresponding to the input voltage and output voltage, it can always supply the desired voltage to the load circuit.
Switching regulators include those that can switch operating modes in accordance with the input voltage. For example, when the input voltage exceeds a prescribed reference level, the regulator enters the so-called back mode. Then, as the input voltage falls below a prescribed reference level, the operating mode is switched to the so-called boost mode. By controlling the switching of the operating mode, it is possible to supply a stable output voltage to the load circuit all the time despite variations in the input voltage. The source of the input voltage in this case is a secondary battery, the output voltage of which falls over time.
FIG. 8 is a circuit diagram illustrating an example of the constitution of a switching regulator that can perform said switching of the operating mode. As shown in the figure, this switching regulator is composed of error detection section 10, pulse-width modulation portion 20, mode control section 30, and switching section 40.
Error detection section 10 is composed of resistive elements R1 and R2 that divide output voltage VOUT with a prescribed voltage division ratio, Gm amplifier GAMP1, and a low-pass filter composed of resistive element R5 and capacitor C1.
Gm amplifier GAMP1 compares the divided voltage obtained by means of resistive elements R1 and R2, that is, the voltage at node N1, with a prescribed reference voltage VREF, and outputs error voltage VER corresponding to the result of said comparison.
Pulse-width modulation portion 20 is composed of npn transistor QN1, resistive elements R3, R4, and comparator COMP1. Said resistive elements R3 and R4 are connected in series between the emitter of transistor QN1 and ground voltage, and error voltage VER is input to the base of transistor QN1.
Transistor QN1 and resistive elements R3 and R4 form an emitter follower. A voltage derived from error voltage VER is output from connecting mode N3 of resistive elements R3 and R4 and is input to the in-phase (noninverting) input terminal (+) of comparator COMP1. On the other hand, sawtooth voltage VTR1 with a prescribed period is input to the inverting input terminal (−) of comparator COMP1. Consequently, pulse-width modulation signal VPWM1 with a duty ratio controlled in correspondence to error voltage VER is output from comparator COMP1. Here, “duty ratio” refers to the proportion of the period that the pulse-width modulation signal VPWM1 is held at the high level.
As shown in the figure, mode control section 30 is composed of PMOS transistor QPM1, NMOS transistor QNM1, buffers DR01, DR02, DR03, DR04, and comparator COMP2.
The gates of transistors QPM1 and QNM1 are both connected to the output terminal of comparator COMP2.
Input voltage VIN is applied to the in-phase (non-inverting) input terminal of comparator COMP2, and reference voltage V2 is input to the inverting input terminal.
Buffers DR01 and DR04 comprise inverters, which output the logical inversion of the input signal. Buffers DR02 and DR03, on the other hand, output the input signal unmodified.
In mode control section 30, when input voltage VIN is higher than reference voltage V2, the output of comparator COMP2 is at the high level. Consequently, PMOS transistor QPM1 is off, while NMOS transistor QNM1 is on. As a result, the input terminals of buffers DR01 and DR02 are kept at the low level. Also, in this case, pulse-width modulation signal VPWM1 is applied to the input terminals of buffers DR03 and DR04.
On the other hand, when input voltage VIN is below reference voltage V2, the output of comparator COMP2 is at the low level. Consequently, PMOS transistor QPM1 is on, while NMOS transistor QNM1 is off. As a result, pulse-width modulation signal VPWM1 is applied to the input terminals of buffers DR01-DR04.
As shown in the figure, switching section 40 is composed of NMOS transistors QNM2, QNM3, QNM4, QNM5 as the switching elements, and coil L1 as the inductive element. These switching elements and inductive element form a so-called H-type bridge.
The output of buffer DR03 is applied to the gate of transistor QNM2, the output of buffer DR04 is applied to the gate of transistor QNM3, the output of buffer DR01 is applied to the gate of transistor QNM4, and the output of buffer DR02 is applied to the gate of transistor QNM5.
Input voltage VIN is applied to the drain of transistor QNM2, and output voltage VOUT is output from the drain of transistor QNM4. Also, output capacitor COUT is connected to the drain of transistor QNM4.
The operating mode of the switching regulator with the aforementioned constitution is controlled according to input voltage VIN by means of mode control section 30. For example, when input voltage VIN is higher than reference voltage V2, transistor QNM1 is kept on, and, corresponding to this state, the input terminals of both buffers DR01 and DR02 are kept at the low level. Consequently, the output terminal of buffer DR01 is kept at the high level, and the output terminal of buffer DR02 is kept at the low level. As a result, in switching section 40, transistor QNM4 is kept on, while transistor QNM5 is kept off. In this case, corresponding to pulse-width modulation signal VPWM1, transistors QNM2 and QNM3 are controlled to turn on and off alternately. Consequently, the switching regulator operates in back mode.
On the other hand, when input voltage VIN is below reference voltage V2, transistor QPM1 is kept on, while transistor QNM1 is kept off. In this case, pulse-width modulation signal VPWM1 is input to the input terminals of each buffer DR01-DR04. Corresponding to this state, as a function of pulse-width modulation signal VPWM1, switching section 40 is controlled to alternately turn on transistors QNM2 and QNM5 and turn off transistors QNM3 and QNM4, and vice versa. That is, in this case, the switching regulator works in boost mode.
Thus, by appropriately switching the operating mode of the switching regulator in accordance with input voltage VIN, it is possible to supply stable voltage VOUT to the load circuit without influence of variations in the level of input voltage VIN at all times.
However, in the aforementioned conventional DC-DC converter, along with the switching of the operating mode, variation in output voltage VOUT takes place, which is undesirable.
In the switching regulator shown in FIG. 8, corresponding to the error of output voltage VOUT with respect to a prescribed reference voltage, pulse-width modulation signal VPWM1 is generated, and the switching element is controlled accordingly. That is, a feedback control loop is formed such that output voltage VOUT is maintained at the desired level. The gain of the feedback control loop (loop gain) varies in company with the switching of the operating mode.
In the following, variations in the output voltage that accompany the switching of the operating mode will be explained with reference to a simulated waveform.
FIG. 9 is a diagram illustrating the waveform of the simulation indicating variations in output voltage VOUT that accompany the switching of the operating mode. The waveform shown in this figure is that obtained when input voltage VIN varies from a level above reference voltage V2 to one below reference V2.
By means of mode control section 30, corresponding to variations in input voltage VIN, the voltage at the output terminal of comparator COMP2, that is, node N5, is switched from a high level to a low level. Accompanying this change, the switching regulator switches the operating mode from back mode to boost mode. The gain of the feedback loop that controls output voltage VOUT in back mode is different from that in boost mode, in that the gain in back mode is higher than that of boost mode. Consequently, the gain of the feedback loop should be changed immediately after the switching of the operating mode from the back mode to the boost mode. However, in the circuit shown in FIG. 8, instead changing the gain immediately, it is changed gradually. Consequently, as shown in FIG. 9, immediately after the switching of the operating mode, the voltages of nodes N2 and N3 temporarily overshoot the ideal level. Consequently, the duty ratio of pulse-width modulation signal VPWM1 output from comparator COMP1 becomes greater than ideal, and output voltage VOUT temporarily rises and exceeds the desired voltage level immediately after the switching of the operating mode.
From the simulation results shown in FIG. 9, one can see that the output voltage immediately after the switching of the operating mode is about 12% higher than the ideal level. Consequently, due to the switching of the operating mode, the output voltage rises temporarily, which may influence the operation of the load circuit.
The purpose of the present invention is to solve the aforementioned problems of the prior art by providing a DC-DC converter characterized in that the DC-DC converter of the present invention allows switching of the operating mode in accordance with variations in the input voltage, and in that corresponding to the switching of the operating mode, the loop gain is corrected in order to minimize variations in the output voltage that accompany the switching of the operating mode, as well as a DC-DC converter drive circuit.